Error correction apparatus, method of correcting an error and method of generating error location data

ABSTRACT

An error correction apparatus comprises an input for receiving data. The received data includes error-check data. The apparatus also includes a processing resource arranged to calculate parity check data. A data store is coupled to the processing resource for storing look-up data for identifying, when in use, a location of an error in the received data. The look-up data is a compressed form of indexed error location data.

FIELD OF THE INVENTION

This invention relates to an error correction apparatus of the typethat, for example, employs look-up data to determine a location of anerror in a bit pattern. This invention also relates to a method ofcorrecting an error of the type that, for example, comprises looking-updata to determine a location of an error in a bit pattern. Thisinvention further relates to a method of generating error location dataof the type that, for example, is accessed to determine a location of anerror in a bit pattern.

BACKGROUND OF THE INVENTION

In the field of data communications, it is known to generate error checkdata based upon a bit pattern to be communicated from a source point toa destination point in a communications network. As an example, a headerof an Asynchronous Transfer Mode (ATM) cell to be transmitted from thesource point to the destination point comprises 40 bits of data. Bits 0to 7 of the header comprise so-called Header Error Check (HEC) databased upon bits 8 to 39 of the header, bits 8 to 39 comprising actualheader data to be communicated. The HEC data is a Cyclic RedundancyCheck 8 (CRC8) value calculated from the actual data (bits 8 to 39).

Upon receipt of the header, the CRC8 value of the data portion of theheader (bits 8 to 39) is re-calculated and used. In the case of ATM, thecalculated CRC8 value is XORed with the HEC data received to calculateparity check data, sometimes known as a syndrome value. For each bitposition of the received data (bits 0 to 39), a unique syndrome valueexists and is typically stored in a look-up table indexed by bitposition. Hence, the unique syndrome value indicates the location of aone-bit error.

Consequently, after calculation of the syndrome value, the syndromevalue is used to search the look-up table for a corresponding location(bit position) of a bit that is in error. The location of the error isthen used to correct the 1-bit error that the received data contains.

However, the table is unsorted and so access of error location data isinefficient, as a linear search method is usually involved. Therefore,for reasons of access speed, the table is sorted by syndrome value and“padded” with unspecified error locations for non-existent syndromevalues, for example −1. The padded look-up table is indexed by syndromevalue, the error location data constituting table entries. Further, thepadded look-up table is known as a “reverse table”.

In order to provide the above error correction, a so-called micro-enginemodule is provided, supported by a microprocessor. However, themicro-engine has limited storage capacity and the padded reverse look-uptable is an inefficient use of storage space. For example, a typicalreverse look-up table for providing CRC8 error correction only has 40out of 256 “specified” entries, i.e. only 15.6% of the entries arespecified, the remaining entries using valuable storage capacity of themicro-engine. Consequently, use of the micro-engine module may not bepossible where constraints on memory space exist.

STATEMENT OF INVENTION

According to the present invention, there is provided an errorcorrection apparatus, a method of correcting an error and a method ofgenerating error location data as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

At least one embodiment of the invention will now be described, by wayof example only, with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of an error correction apparatusconstituting an embodiment of the invention;

FIG. 2 is a schematic diagram of a data compression technique;

FIG. 3 is a schematic diagram of a data structure associated with dataprocessed by the apparatus of FIG. 1; and

FIG. 4 is a flow diagram of a method of correcting an error for theapparatus of FIG. 1.

DESCRIPTION OF PREFERRED EMBODIMENTS

Throughout the following description identical reference numerals willbe used to identify like parts.

Referring to FIG. 1, a communications processor 100 of a Power QuadUniversal Integrated Communications Controller (PowerQUICC™) availablefrom Freescale, Inc. comprises an input 102 coupled to an interface 104,for example an analogue-to-digital converter circuit and, optionally anoptical transducer circuit to convert received optical signals to theelectrical domain in the event that the communications processor iscoupled to an optical communications network (not shown). The interface104 is coupled to a micro-engine circuit 106 comprising microcode 108 tobe executed and a storage space 110 containing compressed look-up data.The micro-engine 106 is coupled to a Central Processing Unit (CPU) 112of the communications processor 100, the CPU 112 being coupled to anoutput 114 of the communications processor 100 for coupling thecommunications processor 100 to, for example an Internet Protocol (IP)interface (not shown).

The compressed look-up data is formed by compressing an original paddedreverse look-up table of a known type, for example the padded reverselook-up table of Table I below.

TABLE I Syndrome errorLoc 0 −1 1 0 2 1 3 −1 4 2 5 −1 6 −1 7 8 8 3 9 −110 −1 11 31 12 −1 13 −1 14 9 15 −1 16 4 17 −1 18 −1 19 −1 20 −1 21 16 2232 23 −1 24 −1 25 −1 26 −1 27 −1 28 10 29 −1 30 −1 31 −1 32 5 33 −1 34−1 35 −1 36 −1 37 −1 38 −1 39 −1 40 −1 41 −1 42 17 43 −1 44 33 45 −1 46−1 47 −1 48 −1 49 39 50 −1 51 −1 52 −1 53 −1 54 −1 55 −1 56 11 57 −1 58−1 59 −1 60 −1 61 −1 62 −1 63 −1 64 6 65 −1 66 −1 67 29 68 −1 69 −1 70−1 71 −1 72 −1 73 −1 74 −1 75 −1 76 −1 77 −1 78 −1 79 −1 80 −1 81 27 82−1 83 −1 84 18 85 −1 86 −1 87 20 88 34 89 −1 90 −1 91 22 92 −1 93 −1 94−1 95 −1 96 −1 97 −1 98 −1 99 −1 100 −1 101 −1 102 −1 103 36 104 −1 105−1 106 −1 107 24 108 −1 109 −1 110 −1 111 −1 112 12 113 −1 114 −1 115 −1116 −1 117 −1 118 −1 119 −1 120 −1 121 −1 122 −1 123 −1 124 −1 125 −1126 −1 127 −1 128 7 129 −1 130 −1 131 −1 132 −1 133 −1 134 30 135 −1 136−1 137 15 138 −1 139 −1 140 −1 141 −1 142 −1 143 −1 144 −1 145 −1 146 −1147 −1 148 −1 149 −1 150 −1 151 −1 152 −1 153 −1 154 −1 155 38 156 −1157 −1 158 −1 159 −1 160 −1 161 −1 162 28 163 −1 164 −1 165 −1 166 −1167 −1 168 19 169 −1 170 −1 171 26 172 −1 173 −1 174 21 175 −1 176 35177 −1 178 −1 179 −1 180 −1 181 −1 182 23 183 −1 184 −1 185 −1 186 −1187 −1 188 −1 189 −1 190 −1 191 −1 192 −1 193 −1 194 −1 195 −1 196 −1197 −1 198 −1 199 14 200 −1 201 −1 202 −1 203 −1 204 −1 205 −1 206 37207 −1 208 −1 209 −1 210 −1 211 −1 212 −1 213 −1 214 25 215 −1 216 −1217 −1 218 −1 219 −1 220 −1 221 −1 222 −1 223 −1 224 13 225 −1 226 −1227 −1 228 −1 229 −1 230 −1 231 −1 232 −1 233 −1 234 −1 235 −1 236 −1237 −1 238 −1 239 −1 240 −1 241 −1 242 −1 243 −1 244 −1 245 −1 246 −1247 −1 248 −1 249 −1 250 −1 251 −1 252 −1 253 −1 254 −1 255 −1

Turning to FIG. 2, the original padded reverse look-up table 200 istransformed to a matrix 202, for example a square matrix, such as a16×16 matrix. The matrix 202 is then compressed into a first array ofdata 204 and a second array of data 206, the first array of data 204being a displacement array, r, and the second array of data 206comprising a plurality of vectors, each vector being two-dimensional.The matrix 202 is compressed according to any suitable algorithm, forexample, as described in “Storing a Sparse Table” (Robert Endre Tarjan,Andrew Chi-Chih Yoo, Communications of the ACM, November 1979, Volume22, Number 11).

The compression technique is such that a mapping exists between thefirst array of data 204 and the second array of data 206. Examples ofthe first array of data 204 and the second array of data 206 are shownin Tables II and III below (use of the term “Table” is not intended tobe limiting and purely for identification purposes), respectively.

TABLE II 0 0 1 17 2 20 3 34 4 36 5 2 6 27 7 5 8 19 9 5 10 10 11 31 12 1913 9 14 0 15 0

TABLE III {224, 13}  {1, 0} {2, 1} {81, 27} {4, 2} {112, 12}  {84, 18}{7, 8} {8, 3} {87, 20} {88, 34} {11, 31} {162, 28}  {91, 22} {14, 9} {214, 25}  {155, 38}  {16, 4}  {168, 19}  {128, 7}  {32, 5}  {171, 26} {21, 16} {22, 32} {174, 21}  {134, 30}  {199, 14}    {0, −1} {137, 15} {28, 10} {42, 17} {176, 35}  {44, 33} {206, 37}  {103, 36}  {49, 39} {646}  {182, 23}  {107, 24}  {67, 29}   {0, −1}   {0, −1} {56, 11}   {0,−1}   {0, −1}   {0, −1}   {0, −1}   {0, −1}   {0, −1}   {0, −1}   {0,−1}   {0, −1}

Operation of the above apparatus will now be described in the context ofa numerical example. In operation, the communications processor 100receives a bit pattern 300 (FIG. 3) comprising a data portion 302 and aHEC portion 304, the bit pattern 300 being a header of an ATM cell. Astransmitted, the data portion 302 was 0x30313233 and the HEC portion 304was 0x69. Upon receipt, the data portion 302 was 0x31313233 and the HECportion was 0x69. Hence, the data portion 302, as received, comprises a1-bit error as compared with the data portion 302 as transmitted.

Referring to FIG. 4, in order to calculate a syndrome value (Step 400),the micro-engine 106 firstly calculates a verifying HEC value for thedata portion 302 of the bit pattern 300 as received:

verHEC=CRC8(0x31313233)=0x7F

As can be seen from the above calculation, the verifying HEC iscalculated using CRC8, though the skilled person will appreciate thatother techniques can be employed for other applications, for exampleCRC16 or CRC32.

Using module 2 addition of the HEC as received and the calculatedverifying HEC, the syndrome value is calculated (Step 400):

S=verHEC ⊕ rxHEC=0x7F ⊕ 0x69=0x16=22

The micro-engine 106 then determines (Step 402) whether the calculatedsyndrome value is equal to zero. If the syndrome value is zero, themicro-engine determines (Step 404) that the data portion 302 of thereceived bit pattern 300 is correct and so the bit pattern istransferred to the CPU 112.

However, if the syndrome value is non-zero, access to the compressedlook-up data is required as the non-zero nature of the calculatedsyndrome value is indicative of the bit pattern 300 as receivedcontaining one or more error. In accordance with the mappings conventionbetween the first array of data 204 and the second array of data 206, anentry, i, of the first array of data 204 is identified (Step 406) byperforming a division operation by n, in this example 16, of thesyndrome value in order to obtain the quotient of the division for useas the entry, i, of the first array of data 204. The micro-engine 106then calculates (Step 406) the remainder, j, of the division of thesyndrome value by n, in this example 16.

The i^(th) entry in the first array of data 204 is then accessed (Step408) by the micro-engine 106 to obtain a corresponding storeddisplacement value, namely 17, and added to the remainder, j,calculated, namely 6:

r[i]=17

j=6

r[i]+j=17+6=23

In accordance with the mapping scheme between the first and second dataarrays 204, 206, the result of the above addition identifies an entry inthe second array of data 206 (Step 410), namely entry number 23 that isdeemed to contain location data identifying the location in the bitpattern 300 of the error, provided the following test is satisfied.

In this regard, the 23^(rd) entry of the second array of data 204 is avector containing a look-up syndrome value and corresponding locationdata. The look-up syndrome value is compared (Step 412) with thecalculated syndrome value. If the look-up syndrome value stored is thesame as the syndrome value calculated, then the syndrome valuecalculated is deemed (Step 414) specified in the original look-up table200 upon which the first and second arrays of data 204, 206 are basedand so the location data, in this example 32, is used. If, however, thelook-up syndrome value and the calculated syndrome values are not thesame, then the syndrome value calculated is deemed (Step 416)unspecified in the original look-up table 200 and the error in the bitpattern 300 cannot be corrected (Step 418) by the micro-engine 106, forexample due to the bit pattern 300 containing more than one error

When the calculated syndrome value is deemed (Step 414) specified, theerror location in bit pattern 300 is found. If the one bit error occursin the HEC portion 304, the data portion 302 is error free and so noerror correction to the data portion 302 is needed. If the one bit-erroroccurs in the data portion 302, a correcting bit pattern needs begenerated to correct (Step 420) the error. Consequently, a leastsignificant bit of the following initial bit pattern is then shifted tothe right by (32 (the location of the error)−8) bit positions (due tothe first 8 bits of the header relating to the HEC) in order to yield acorrecting bit pattern:

errorPattern=0x00000001<<(32−8)=0x01000000

The micro-engine 106 then performs module 2 addition of the data portion302 as received with the correcting bit pattern:

rxData=0x31313233 ⊕ 0x01000000=0x30313133

The 1-bit error in the received bit pattern is thus corrected and thenforwarded to the CPU 112. The above process is then repeated forsubsequently received ATM headers.

Although the above example has been described in the context of an ATMheader, the skilled person will appreciate that the above technique canbe applied to other bit patterns, for example an IP packet.

It is thus possible to provide a method and apparatus that canfacilitate access of error location data with sufficient speed whilstemploying look-up data that is economic with storage space of themicro-engine. In this respect, the compressed look-up data only requires120 bytes of storage space, representing a 53% saving in storage spaceover the original padded look-up table. Of course, the above advantagesare exemplary, and these or other advantages may be achieved by theinvention.

The invention may also be implemented in a computer program for runningon a computer system, at least including code portions for performingsteps of a method according to the invention when run on a programmableapparatus, such as a computer system or enabling a programmableapparatus to perform functions of a device or system according to theinvention. Such a computer program may be provided on a data carrier,such as a CD-rom or diskette, stored with data loadable in a memory of acomputer system, the data representing the computer program. The datacarrier may further be a data connection, such as a telephone cable or awireless connection.

In the foregoing specification, the invention has been described withreference to specific examples of embodiments of the invention. It will,however, be evident that various modifications and changes may be madetherein without departing from the broader spirit and scope of theinvention as set forth in the appended claims. For example, theinvention is not limited to physical devices or units implemented innon-programmable hardware but can also be applied in programmabledevices or units able to perform the desired device functions byoperating in accordance with suitable program code. Furthermore, thedevices may be physically distributed over a number of apparatuses,while functionally operating as a single device. Also, devicesfunctionally forming separate devices may be integrated in a singlephysical device. Further, the skilled person will appreciate that notall advantages stated above are necessarily achieved by embodimentsdescribed herein.

In the claims, any reference signs placed between parentheses shall notbe construed as limiting the claim. The word ‘comprising’ does notexclude the presence of other elements or steps then those listed in aclaim. Furthermore, the words ‘a’ and ‘an’ shall not be construed aslimited to ‘only one’, but instead are used to mean ‘at least one’, anddo not exclude a plurality. The mere fact that certain measures arerecited in mutually different claims does not indicate that acombination of these measures cannot be used to advantage.

1. An error correction apparatus comprising: an input for receiving datathat includes error-check data; a processing resource arranged tocalculate parity check data; and a data store coupled to the processingresource and arranged to store look-up data for identifying, when inuse, a location of an error in the received data, wherein the look-updata is a compressed form of indexed error location data.
 2. Anapparatus as claimed in claim 1, wherein the processing resource isarranged to calculate the parity check data using the data including theerror-check data.
 3. An apparatus as claimed in claim 1, wherein thecompressed form of the indexed error location data comprises a firstarray of data and a second array of data.
 4. An apparatus as claimed inclaim 3, wherein the first array of data comprises identifying data toidentify data within the second array of data to be accessed.
 5. Anapparatus as claimed in claim 3, wherein a mapping exists between theuncompressed indexed error location data and the first array of data andthe second array of data.
 6. An apparatus as claimed in claim 3, whereinthe first array of data comprises displacement data.
 7. An apparatus asclaimed in claim 3, wherein the second array of data comprises aplurality of vectors.
 8. An apparatus as claimed in claim 7, wherein afirst dimension of each vector constitutes an index and a seconddimension of each vector identifies an error location.
 9. An apparatusas claimed in claim 1, wherein the error location data is indexed byparity check value.
 10. An apparatus as claimed in claim 1, wherein thecompressed form of the indexed error location data is a compression of amatrix representation of a table of the indexed error location data. 11.An apparatus as claimed in claim 1, wherein the compressed form of theindexed error location data is formed using a matrix compressionalgorithm.
 12. An apparatus as claimed in claim 1, wherein the receiveddata is a header of a data structure.
 13. An apparatus as claimed inclaim 1, wherein the received data is a part of an Asynchronous TransferMode cell.
 14. A method of correcting an error in data that includeserror-check data, the method comprising the steps of: generating paritycheck data from the data; accessing look-up data to identify a locationof an error in the data, wherein access of the look-up data being accessof a compressed form of indexed error location data.
 15. A method ofgenerating error location data, the method comprising the steps of:generating a table of error location data indexed by parity check value;forming a matrix from the table of error location data; and compressingthe matrix to form a first array of data and a second array of data. 16.A method as claimed in claim 15, wherein a mapping exists between thetable of error location data and the first array of data and the secondarray of data.
 17. A method as claimed in claim 15 wherein the secondarray of data comprises a plurality of vectors.
 18. A method as claimedin claim 17, wherein a first dimension of each vector constitutes anindex and a second dimension of each vector identifies as errorlocation.
 19. A method as claimed in claim 15, wherein the matrix iscompressed using a matrix compression algorithm to form the first arrayof data and the second array of data.
 20. A computer program product,including program code portions for performing operations when run on aprogrammable apparatus, the operations comprising: generating paritycheck data from data; accessing look-up data to identify a location ofan error in the data, wherein access of the look-up data being access ofa compressed form of indexed error location data.